•  Superjunction MOSFET

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• 为了一些客户的紧急需求，英国工厂存有部分现货！

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• 欢迎您来电咨询更详细的产品信息！

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• 为满足更多客户要求，我们也提供顶层145nm/200nm/300nm/340nm/365nm/400nm 等规格SOI硅片。

SOI 规格：

1       Bonded SOI wafer (绝缘硅上键合硅片）

         For 4”(100mm）, 5”（125mm）, 6”（150mm）

  ---- Handle wafer minimum 300um maximum 1000um,

  ---- Buried Oxide, minimum 0.1 um, maximum 4 um,

  ---- Device layer minimum 2 um, max 500 um.

         For 8"（200mm）

  ---- Handle thickness minimum 500um and maximum 675um,

  ---- Buried Oxide minimum 0.1 um, maximum 4 um,

  ---- Device layer minimum 5 um, maximum 500 um.

2-     Si-Si direct wafer bonding (replacement for epi) 硅-硅直接键合，可替代外延片

         100mm, 125mm, 150mm and 200mm, thickness as specified above.

3-     Engineered SOI, Double SOI (DSOI), Trench Isolation SOI (dielectric isolation),

        Cavity SOI (for pressure sensor, gyro and accelerometer sensor, microfludic etc.)

        and finally Through Silicon Via (TSV)   

 ----  Cavity SOI- Bonded SOI or Silicon DWB wafers with cavities performed within the wafer

 ---- Multiple SOI 2 or 3 or more layers of SOI designed around your process

 ---- Structured wafers silicon wafers or SOI with buried electrode layers, vias, interconnect already incorporated

4-    SOI + Trench & Refill

        Features

       a.  Significant die shrink compared to conventional dielectric isolation(DI) or junction isolation

       b.  Bulk quality top silicon layer

       c.  Total device-to-device isolation

       d.  Lower substrate capacitance than bulk

       e.  Fully flexible specification on SOI, Trench and refill parameters